Advanced Vector Extensions

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Advanced Vector Extensions ( AVX , also known as Sandy Bridge New Extension ) is an extension for the x86 instruction set architecture for the proposed Intel and AMD microprocessors by Intel in March 2008 and was first powered by Intel with delivery of Sandy Bridge processors in Q1 2011 and later by AMD with Bulldozer processor shipments in Q3 2011. AVX provides new features, new instructions and new coding schemes.

AVX2 extends most integer commands to 256 bits and introduces a fused multiply-accumulate (FMA) operation. AVX-512 extends AVX to 512-bit support using the new EVEX prefix prefix by July 2013 and first powered by Intel with Knights Landing processor, delivered in 2016.

Video Advanced Vector Extensions

Advanced Vector Extensions

AVX uses sixteen YMM registers. Each YMM list contains:

• eight single-point floating-point 32-bit or
precision numbers
• four-digit 64-bit floating point precision.

The width of the SIMD register file increases from 128 bits to 256 bits, and is replaced from XMM0-XMM7 to YMM0-YMM7 (in x86-64 mode, YMM0-YMM15). In processors with AVX support, legacy SSE instructions (previously operated on 128-bit XMM registers) can be extended using the VEX prefix to operate at 128 bits lower than the YMM register.

AVX introduces a three-operand SIMD instruction format, where the destination registers are different from the two source operands. For example, SSE instructions using conventional two-operand forms aÃ, = aab can now use a non-destructive three-operand form cÃ, = Ã, ab , preserving both operand sources. The three-operand AVX format is limited to instructions with the SIMD operand (YMM), and does not include instructions with general purpose registers (eg EAX). Such support will appear first in AVX2.

SIMD memory operand synchronization requirements are relaxed.

The new VEX coding scheme introduces a new set of code prefixes that extend opcode space, allowing instructions to have more than two operands, and allowing the vector register of SIMD to be longer than 128 bits. VEX prefixes can also be used on legacy SSE instructions giving them three operands, and making them interact more efficiently with AVX instructions without the need for VZEROUPPER and ZEROALL.

The AVX instruction supports 128-bit and 256-bit SIMDs. The 128-bit version can be useful for improving old code without widening vectorization, and avoiding penalties from SSE to AVX, they are also faster on some early AMD AMD implementations. This mode is sometimes known as AVX-128.

New instructions

This AVX Hint is an addition that is a 256-bit extension of an inherited 128-bit SSE instruction; most can be used on 128-bit and 256-bit operands.

CPU with AVX

• Intel
  • Sandy Bridge Processor, Q1 2011
  • Sandy Bridge Processor E, Q4 2011
  • Ivy Bridge Processor, Q1 2012
  • Ivy Bridge E processor, Q3 2013
  • Haswell Processor, Q2 2013
  • Haswell processor E, Q3 2014
  • Broadwell Processor, Q4 2014
  • Broadwell E processor, Q2 2016
  • Skilake Processor, Q3 2015
  • Kaby Lake Processor, Q3 2016 (ULV phone)/Q1 2017 (desktop/mobile)
  • Skylake-X Processor, Q2 2017
  • Coffee Lake Processor, Q4 2017
  • The Cannon Lake processor (microarchitecture), expected by 2018
  • The Cascade Lake procession, expected by 2018
  • Ice Lake processor, expected by 2018

Note: Not all CPUs of registered families support AVX. Generally, the CPU with the commercial denomination "Core i3/i5/i7" supports it, while CPU "Pentium" and "Celeron" do not have it.

• AMD:
  • Jaguar-based and newer processors
  • Puma-based and newer processors
  • "Heavy Equipment" processor
    • Bulldozer based processor, Q4 2011
    • Piledriver-based processor, Q4 2012
    • Transmitter-based processor, Q1 2014
    • Excavator-based and newer processors, 2015
  • Zen-based processor, Q1 2017
  • Zen-based processor, Q2 2018

Problems about compatibility between future Intel and AMD processors are discussed under the XOP instruction set.

Support compiler and assembler

GCC starts with version 4.6 (although there are 4.3 branches with certain support) and Intel Compiler Suite starting with version 11.1 supports AVX. Visual Studio 2010/2012 compiler supports AVX via intrinsic and/arch: AVX switch. Open64 compiler version 4.5.1 supports AVX with -mavx flag. Absoft supports with -mavx flag. PathScale supports through the -mavx flag. The Free Pascal compiler supports AVX and AVX2 with switches -CfAVX and -CfAVX2 from version 2.7.1. The Pascal Vector compiler supports AVX via the -cpuAVX32 flag. The GNU Assembler inline assembly function (GAS) supports this instruction (accessible via GCC), as do Intel primitives and Intel inline assemblers (highly compatible with GAS, though more commonly in local reference handling in inline code). Other assemblers like MASM VS2010 version, YASM, FASM, NASM and JWASM.

Operating system support

AVX adds a new register-state through a 256-bit wide YMM register file, so clear operating system support is required to store and restore well-expanded AVX registers between context switches. The following operating system versions support AVX:

• Apple OS X: Support for AVX added in update 10.6.8 (Snow Leopard) released on June 23, 2011.
• DragonFly BSD added support in early 2013.
• FreeBSD in the patch submitted on January 21, 2012, which is included in the stable release of 9.1
• Linux: supported since kernel version 2.6.30, released on June 9, 2009.
• OpenBSD added support on March 21, 2015.
• Solaris 10 Update 10 and Solaris 11
• Windows: supported on Windows 7 SP1 and Windows Server 2008 R2 SP1, Windows 8, Windows 10
• Windows Server 2008 R2 SP1 with Hyper-V requires hotfixes to support AMD AVX processors (Opteron 6200 and 4200 series), KB2568088

Maps Advanced Vector Extensions

Advanced Vector Extension 2

Advanced Vector Extensions 2 (AVX2), also known as Haswell New Instructions , is an extension of the AVX instruction set introduced in Haswell Intel's microarchitecture. AVX2 makes the following additions:

• expansion of most SSE integer vectors and AVX instructions to 256 bits
• bit manipulation for general purpose and multiply
• Collect support, allowing vector elements to load from non-contiguous memory locations
• DWORD- and any-to-permutation QWORD-granularity
• vector shift.

Sometimes other extensions using different cpuid flags are considered part of AVX2; these instructions are listed on their own page and not below:

• three operands converge accumulate-stacking support (FMA3)

New directions

CPU with AVX2

• Intel
  • Haswell processor, Q2 2013
  • Haswell processor E, Q3 2014
  • Broadwell Processor, Q4 2014
  • Broadway E processor, Q3 2016
  • Skilake Processor, Q3 2015
  • Kaby Lake Processor, Q3 2016 (ULV phone)/Q1 2017 (desktop/mobile)
  • Skylake-X Processor, Q2 2017
  • Coffee Lake Processor, Q4 2017
  • The Cannon Lake processor, expected by 2018
  • The Cascade Lake procession, expected by 2018
  • Ice Lake processor, expected by 2018
• AMD
  • Excavator and newer processors, Q2 2015
  • Zen Processor, Q1 2017

src: simplecore.intel.com

AVX-512

AVX-512 is a 512-bit extension to 256-bit Advanced Vector Extensions of SIMD instructions for the x86 instruction set architecture proposed by Intel in July 2013, and is scheduled to be backed in 2015 with Intel Knights Landing processors.

The AVX-512 instruction is encoded with a new EVEX prefix. It allows 4 operands, 7 new 64-bit opmask registers, scalar memory mode with automatic broadcasting, explicit rounding controls, and compressed-mode memory addressing modes. The file register width increases to 512 bits and the total number of registers increases to 32 (register ZMM0-ZMM31) in x86-64 mode.

AVX-512 consists of several extensions not all intended to be supported by all processors that implement them. The instruction set consists of the following:

• AVX-512 Foundation - adds several new instructions and extends at most 32-bit and 64-bit floating point SSE-SSE4.1 and AVX/AVX2 instructions with EVEX coding schemes to support 512-bit registers, operations masks, parameter broadcasting, and rounding controls and embedded rounding controls
• AVX-512 Conflict Detection Instructions (CD) Ã, - efficient conflict detection to allow more loops to be vectored, supported by Knights Landing
• AVX-512 Exponential and Reciprocal Instructions (ER) Ã, - exponential and reciprocal operations designed to help implement transcendental operations, powered by Knights Landing
• AVX-512 Prefetch Instructions (PF) Ã, - new prefetch capability, powered by Knights Landing
• AVX-512 Long Vector Extension (VL) Ã, ā € "extends most AVX-512 operations to operate on XMM (128-bit) and YMM (256-bit) registers (including XMM16-XMM31 and YMM16-YMM31 in x86- Mode 64)
• AVX-512 Byte and Word Instruction (BW) Ã, - expand AVX-512 to include 8-bit and 16-bit integer operations
• AVX-512 Doubleword and Quadword Instruction (DQ) Ã, - enhanced 32-bit and 64-bit integer operations
• AVX-512 Integer Fused Multiply Add (IFMA) - combines numbers at once for 512-bit integers.
• AVX-512 Vector Byte Manipulation Instructions (VBMI) adds a vector byte permutation instruction that is not present in AVX-512BW.
• AVX-512 Vector Neural Network Word variable precision instruction (4VNNIW) - vector instruction for in-depth learning.
• AVX-512 Fused Multiply Accumulation Packed Single precision (4FMAPS) - vector instruction for in-depth learning.
• VPOPCNTDQ - number of bits set to 1.
• VPCLMULQDQ - multiplication less than quadwords.
• AVX-512 Vector Neural Network Instructions (VNNI) - vector instruction for in-depth learning.
• AVX-512 Galois Field New Instructions (GFNI) - vector instruction to calculate Galois Field.
• AVX-512 Vector AES instructions (VAES) - vector instruction for AES encoding.
• AVX-512 Vector Byte Instructions 2 manipulation (VBMI2) - byte/word load, save and compose with shift.
• AVX-512 Bit (BITALG) algorithm - bit/word bit manipulation instructions extend VPOPCNTDQ.

Only the AVX-512F (AVX-512 Foundation) core extension is required by all implementations, although all current processors also support CD (conflict detection); computing processors will also support ER, PF, 4VNNIW, 4FMAPS, and VPOPCNTDQ, while desktop processors will support VL, DQ, BW, IFMA, VBMI, VPOPCNTDQ, VPCLMULQDQ, etc.

Updated SSE/AVX instructions in AVX-512F using the same mnemonics as AVX versions; they can operate on 512 bit ZMM registers, and will also support XMM/YMM 128/256 bit registers (with AVX-512VL) and byte operand, word, doubleword and quadword integer (with AVX-512BW/DQ and VBMI).

CPU with AVX-512

Compiler that supports AVX-512

• GCC 4.9 and later
• Clang 3.9 and later
• ICC 15.0.1 and later
• Microsoft Visual Studio 2017 C Compiler
• Java 9

src: slideplayer.com

Apps

• Suitable for floating point intensive calculations in multimedia, scientific and financial applications (AVX2 adds support for integer operations).
• Increases parallelism and throughput in floating point SIMD calculations.
• Reduce the register load due to non-destructive instructions.
• Improve the performance of Linux RAID software (AVX2 required, AVX not enough)

Software

• Blender uses AVX2 in the rendering engine cycle.
• OpenSSL uses AVX and AVX2 cryptography functions optimized since version 1.0.2.
• Prime95/MPrime, the software used for GIMPS, started using AVX instructions since version 27.x.
• dnetc, the software used by distributed.net, has an AVX2 core available for its RC5 project and will soon release one for its OGR-28 project.
• Einstein @ Home uses AVX in some of their distributed applications that are looking for gravitational waves.
• RPCS3, an open source PlayStation 3 emulator, uses AVX2 and AVX-512 instructions to emulate PS3 games.
• Network Device Interface, NDIÃ,® is an IP video/audio protocol developed by NewTek for live broadcast productions, using AVX and AVX2 for improved performance.

src: www.sigarch.org

See also

• Memory Protection Extension

src: slideplayer.com

References

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External links

• Intel Intrinsic Guide

Source of the article : Wikipedia